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PDF) On the Generation of Functional Test Programs for the Cache Replacement Logic
PDF) Symmetry Measure for Memory Test and Its Application in BIST Optimization
PDF) Memory testing with a RISC microcontroller
Dimitris Magos's research works | University of West Attica, Athens (TEIATH) and other places
ERCIM News 96 by Peter Kunz - Issuu
PDF) UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations
PDF) Extending Internet into Space – ESA DTN Testbed Implementation and Evaluation
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PDF) Delay-Insensitive Cell Matrix.
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) Detection of Delay Faults in Memory Address Decoders
PDF) New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults
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PDF) On the generation of pseudo-deterministic two-patterns test sequence with LFSRs.
PDF) An adaptive BIST to detect multiple stuck-open faults in CMOS circuits
PDF) Accumulator-Based Weighted Pattern Generation.
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
IVML > People > Phivos Mylonas
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PDF) Modeling and Simulation of Efficient March Algorithm for Memory Testing
PDF) Survival analysis for modeling critical events that communities may undergo in dynamic social networks
PDF) A domain-specific approach for software development on Manycore platforms
PDF) Test Embedding with Discrete Logarithms
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PDF) Efficient Test Compaction for Pseudo-Random Testing
PDF) High-Level Test Synthesis for Delay Fault Testability
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